1. Field of the Invention
The present invention relates to a solid-state image capturing apparatus and an electronic information equipment, and in particular, to a solid-state image capturing apparatus equipped with a pixel power regulator and an electronic information equipment using such a solid-state image capturing apparatus.
2. Description of the Related Art
In conventional solid-state image capturing apparatuses, an external source voltage VANA, which is supplied from the outside of the chips that constitute the solid-state image capturing apparatus, is generally used as voltage to be supplied to pixels.
FIG. 6 is a block diagram illustrating a conventional solid-state image capturing apparatus, showing a configuration for supplying an external source voltage to pixels and a vertical driving circuit.
A solid-state image capturing apparatus 200 includes a pixel array (PIX AREA) 210 where pixels are arranged in a matrix; a vertical signal line (output signal line) Vp provided to correspond to each pixel column of the pixel array for reading out a voltage signal from each pixel of a corresponding pixel column; a vertical scanning circuit (DECV) 220 for selecting a specific pixel row in the pixel array to drive the pixels of the selected pixel row; a horizontal scanning circuit (DECH) 230 for processing a voltage signal read out from each pixel of the selected pixel row to the corresponding vertical signal line Vp, to be output as a pixel signal Sp; and a load (PIXLOAD) 240 connected to the vertical signal line so as to flow a constant current to each vertical signal line Vp. Herein, a pad P1 is a power source pad to which the external source voltage VANA is applied.
FIG. 7 is a diagram illustrating a circuit configuration of one pixel in the pixel array described above and a vertical driving circuit connected to one pixel in a vertical scanning circuit.
A pixel Px includes: a photoelectric conversion element (photodiode) PD for performing a photoelectric conversion to generate a signal charge; an electric charge accumulating section (floating diffusion) FD for accumulating the signal charge generated at the photodiode PD; a transfer transistor Ttr connected between the photodiode PD and the electric charge accumulating section FD for transferring the signal charge generated at the photodiode to the electric charge accumulating section FD; a reset transistor Rtr for resetting the signal charge accumulated in the electric charge accumulating section FD; an amplifying transistor Atr for amplifying an electric potential of the electric charge accumulating section FD to be output to the vertical signal line Vp; and a selection transistor Str connected between a drain of the amplifying transistor and the source voltage VANA for controlling the supply of the source voltage to the amplifying transistor.
In addition, a constant current source Pw is connected between the vertical signal line Vp, described above, and ground. A horizontal readout circuit 230a for reading out the voltage signal read out to the vertical signal line Vp is connected to the vertical signal line Vp that corresponds to each pixel column. This horizontal readout circuit 230a is a circuit portion that corresponds to one pixel column in the horizontal scanning circuit 230.
In addition, the pixel Px is connected to a vertical driving circuit 220a for driving the pixel, and the vertical driving circuit 220a is a circuit portion corresponding to one pixel row in the vertical scanning circuit described above. The vertical driving circuit 220a includes a driver Sdr for driving a selection signal line connected to a gate of the selection transistor Str described above; a driver Rdr for driving a reset signal line connected to a gate of the reset transistor Rtr described above; and a driver Tdr for driving a transfer signal line connected to a gate of the transfer transistor Ttr described above.
Next, the operation will be described.
When the pixel power VANA is externally applied to the power pad P1, the externally supplied pixel power VANA is supplied to the pixel array 210 and the vertical driving circuit 220a inside the vertical scanning circuit (DECV) 220.
In each pixel of the pixel array, a signal charge is generated by the photodiode PD; a signal voltage corresponding to the signal charge and a reset voltage are read out to the vertical signal line Vp by the vertical scanning circuit 220; and further, the signal voltage and the reset voltage read out to the vertical signal line Vp are processed by the horizontal scanning circuit 230 and outputted as a pixel signal Sp of each pixel.
Next, the readout operation by the vertical driving circuit will be briefly described with reference to FIG. 7.
The gate (reset signal line) of the reset transistor Rtr is driven by the driver Rdr. When the reset transistor Rtr is turned on, the electric potential of the electric charge accumulating section FD is reset by a reset voltage. Subsequently, the gate (selection signal line) of the selection transistor Str is driven by the driver Sdr. When the selection transistor Str is turned on, the source voltage VANA is applied to the drain of the amplifying transistor Atr. Consequently, the voltage of the electric charge accumulating section FD is amplified by the amplifying transistor Atr and is read out to the vertical signal line Vp as a reset voltage. In this state, when the gate (transfer signal line) of the transfer transistor Ttr is driven by the driver Tdr and thereby the transfer transistor Ttr is turned on, the signal charge generated at the photodiode PD is transferred to the electric charge accumulating section FD, and the electric potential of the electric charge accumulating section FD turns to be a signal level corresponding to the signal charge. This signal level is amplified by the amplifying transistor Atr and is output as a signal voltage.
In parallel with such an operation of outputting the electric potential level of the electric charge accumulating section FD to the vertical signal line Vp, an operation for reading out an electric potential level of the vertical signal line Vp is performed in the horizontal readout circuit 230a. That is, the horizontal readout circuit 230a reads out the rest voltage outputted to the vertical signal line Vp, and further, reads out the signal voltage outputted to the vertical signal line Vp and outputs the difference voltage as the pixel signal Sp.
In such a solid-state image capturing apparatus, however, noise from external systems is superimposed to the externally supplied source voltage. The noise is supplied to the pixel Px and even to each driver inside the vertical driving circuit 220a, namely the driver Rdr for driving the reset transistor Rtr, the driver Tdr for driving the electric charge transfer transistor Ttr, the driver Sdr for driving the pixel selection transistor Str, and the like. Consequently, deterioration in picture quality (horizontal line noise) occurs due to the noise of the pixel power.
As a method for preventing such a problem, Reference 1 discloses a CMOS image sensor equipped with a charge pump boosting circuit. Based on Reference 1, a method is easily conceivable where a voltage, which is generated by a boosting circuit with a band-gap reference voltage (BGR) and the like as a reference voltage and is not dependent on a source voltage, is used as a source voltage of a pixel and a vertical driving circuit.
FIG. 8 is a diagram illustrating a solid-state image capturing apparatus that includes a circuit configuration that achieves such a method.
A solid-state image capturing apparatus 200a shown in FIG. 8 is the solid-state image capturing apparatus 200 shown in FIG. 7 equipped with a boosting circuit (charge pump) 280, and other configurations thereof are identical to the solid-state image capturing apparatus 200 shown in FIG. 7.
The boosting circuit 280 is provided with source voltage from an external power source. In the boosting circuit 280, a voltage that does not depend on an external source voltage is generated as a source voltage for a pixel and a vertical driving circuit, based on a reference voltage Vref generated by using band gaps of the transistors.
In this case, the influence of the noise superimposed from the external systems to the power source can be eliminated. However, as the current required for driving the pixel is supplied from the boosting circuit (charge pump) 280, the boosting circuit is required with a capability for supplying a large amount of current. That results in the increase of the layout area of the boosting circuit (charge pump) 280, and further, the increase of the power consumption by the boosting circuit (charge pump) 280.
Reference 1: Japanese Laid-Open Publication No. 2006-19971